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dc.contributor.authorCarvino, Anthony
dc.contributor.authorCoppola, Thomas
dc.date.accessioned2018-05-29T18:53:50Z
dc.date.available2018-05-29T18:53:50Z
dc.date.issued2018-05
dc.identifier.urihttp://hdl.handle.net/1951/70255
dc.description.abstractReconfigurable logic devices, such as Field Programmable Gate Arrays (FPGA), offer ideal platforms for the dynamic implementation of embedded, low power, massively parallel neuromorphic computing systems. Though somewhat inferior to Application Specific Integrated Circuits (ASIC) with regard to performance and power consumption, FPGAs compensate for this small discrepancy by providing a versatile and reconfigurable fabric that is capable of implementing the logic of any valid digital system. Using the Xilinx ZYNQ 7 Series All Programmable System on Chip, as actuated and exposed by the PYNQ-Z1 Development Environment, the present work aims to provide a demonstration of the efficacy of the heterogeneous approach to neuromorphic computing. We expose a hardware implementation of a configurable neural layer to the processing system as a software module and handle its data and parameter flow at the productivity level using Python. Results indicate a nearly negligible increase (3%) in dynamic power consumption over that consumed by the processing system alone. Further, by specifically utilizing the embedded Digital Signal Processing (DSP) and memory blocks of the ZYNQ device, we employ a relatively large percentage of these resources (13% and 11%, respectively), but consume only 5% of the Lookup Table (LUT) fabric, preserving the vast majority of resources for the implementation of other, perhaps complementary systems. Although the successfully completed heterogeneous system demonstrates that it possesses the capacity to learn, the proper training of neuromorphic systems such as this Artificial Neural Network (ANN) is a project in and of itself, and so the focus herein is more on the heterogeneous system engineered than on the prototypical application selected, which is text-independent speaker verification using Mel Frequency Cepstral Coefficients (MFCC) and log-filterbank energies as features. Fast, low power, small footprint neuromorphic systems are desirable for embedded applications that might improve the state of their art by exploiting applied artificial intelligence. Systems such as the configurable neural layer developed herein – which make use of the naturally versatile, low power, and high-performance FPGA in conjunction with a microprocessor control system – seem not only technologically viable, but well suited for handling intelligent embedded applications.en_US
dc.language.isoen_USen_US
dc.rightsAttribution-NonCommercial-NoDerivs 3.0 United States*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/3.0/us/*
dc.subjectComputer engineeringen_US
dc.subjectNeuromorphic computing systemsen_US
dc.subjectHonors Thesesen_US
dc.subjectHeterogeneous systemsen_US
dc.subjectReconfigurable computingen_US
dc.subjectLow power embedded systemsen_US
dc.subjectSpeaker verificationen_US
dc.subjectSpeech processingen_US
dc.subjectFeature extractionen_US
dc.subjectResearch Subject Categories::TECHNOLOGY::Information technology::Computer engineeringen_US
dc.titleHeterogeneous implementation of an artificial neural networken_US
dc.typeThesisen_US


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Attribution-NonCommercial-NoDerivs 3.0 United States
Except where otherwise noted, this item's license is described as Attribution-NonCommercial-NoDerivs 3.0 United States