AbstractCopper is the primary metal used in integrated circuit manufacturing of today. Even though copper
is face centered cubic it has significant mechanical anisotropy depending on the crystallographic orientations. Copper metal lines in integrated circuits are polycrystalline and typically have lognormal grain size distribution. The polycrystalline microstructure is known to impact the reliability and must be considered in modeling for better understanding of the failure mechanisms. In this work, we used Voronoi tessellation to model the polycrystalline microstructure with lognormal grainsize distribution for the copper metal lines in test structures. Each of the grains is then assigned an orientation with distinct probabilistic texture and corresponding anisotropic elastic constants based on the assigned orientation. The test structure is then subjected to a thermal stress. A significant variation in hydrostatic stresses at the grain boundaries is observed by subjecting the test structure to thermal stress due to the elastic anisotropy of copper. This introduces new weak points within the metal interconnects leading to failure. Inclusion of microstructures and corresponding anisotropic properties for copper grains is crucial to conduct a realistic study of stress voiding, hillock formation, delamination, and electromigration phenomena, especially at smaller nodes where the anisotropic effects are significant.