32-bit Superconductor Integer and Floating-Point Multipliers

Abstract

The objective of this dissertation is to design and evaluate ultra-fast energy-efficient 32-bit integer and single-precision floating-point multipliers implemented with Rapid Single Flux Quantum (RSFQ) superconductor technology. Our goals in both multiplier designs were to design a wide datapath multipliers operating in 10 GHz+ frequencies with lowest possible latency and complexity below 100k Josephson junctions when implemented with Hypres 1.5 um 4.5 kA/cm2 fabrication process. To achieve this goal, various design techniques such as synchronous pipelining, asynchronous co-flow, and wave-pipelining are analyzed and applied throughout the design process. First, we have a brief look at CMOS computing with its power and clock frequency challenges. Then, superconductor technology is introduced, followed by a description of RSFQ logic. Next, traditional design and sequencing techniques for multiplier will be discussed. After a brief review of existing superconductor multipliers, the cell-level design of our 32-bit integer and floating-point multipliers will be presented. The microarchitectures and implementations of the 32-bit multipliers are discussed in detail along with the choice of sequencing techniques used. Our multipliers were designed and evaluated using a SBU VHDL RSFQ cell-library tuned to the Hypres 1.5 um 4.5kA/cm2 fabrication process. The simulation results for the 32-bit integer and floating-point multipliers will be presented along with statistical data about each design. Finally, we will present the design and experimental test results of an 8-bit integer RSFQ multiplier implemented with the Japanese CONNECT cell library and fabricated with ISTEC 1.0 um 10 kA/cm2 technology.