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    POWER DISTRIBUTION IN TSV BASED 3-D PROCESSOR-MEMORY STACKS

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    Satheesh_grad.sunysb_0771M_10918.pdf (1.387Mb)
    Date
    1-May-12
    Author
    Satheesh, Suhas Mysore
    Publisher
    The Graduate School, Stony Brook University: Stony Brook, NY.
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    Abstract
    Three primary techniques for manufacturing through silicon vias (TSVs), via-first, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this work. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to number of TSVs and decoupling capacitance.
    Description
    55 pg.
    URI
    http://hdl.handle.net/1951/59853
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    • Stony Brook Theses & Dissertations [SBU] [1955]

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