Semiconductor devices are becoming increasingly more complex as the number of transistors increases in the same Integrated Circuit (IC) area. Due to the complexity in design; processing and packaging of the device plays a crucial role in the IC fabrication. Package induced residual stress are not only detrimental to device performance but can also lead to device failure. We propose a non-destructive method to determine the complete stress state at each point on a packaged Silicon device. Surface and edge defect created as a result of various manufacturing steps were characterized using different techniques, primarily X-ray diffraction topography, optical microscopy, SEM and TEM. Residual stress plays an important role in the performance and lifetime of single crystal device material. Here we present a novel technique using white beam synchrotron X-ray diffraction reticulography, Stress Mapping and Analysis via Ray Tracing (SMART) in order to determine residual stress level at an array of points over the entire crystal area. This method has a unique advantage compared with other stress measurement technique in that it can evaluate all six components of the stress tensor. The underlying experimental technique is based on white beam synchrotron X-ray diffraction topography and ray tracing. An array of X-ray micro-beam is illuminated on the single crystal sample and multiple reflections (reticulographs) are recorded simultaneously on a photographic film. Crystallographic plane normal vector at the location of each micro-beam in the crystal is calculated. The variation of the plane normal vector direction is due to residual strain (both sheer and dilatational) present in the crystal. By considering three different diffracting planes and corresponding reticulograph a complete state of stress is calculated. Principle, applications and limitations are discussed. White beam synchrotron reticulography is used in reflection geometry to evaluate complete residual stress tensor as a function of depth in a single crystal material. This novel technique, an extension of SMART technique is developed to determine stress tensor components at various depths within the crystal. In reflection geometry penetration depth is controlled by manipulating the geometrical parameters such as incident angle. Data is obtained from various penetration depth, which represents exponentially decaying weighted average of actual stress value or in other words this stress profile is Laplace transform of real stress profile. Mathematical procedure is described to determine real stress profile from Laplace profile. To demonstrate this method, a packaged semiconducting Silicon die is used and its complete stress tensor profile is generated. This method has demonstrated the capability of determining all six components of stress as a function of depth in the crystal. Experimental procedure, theoretical basis and mathematical methods along with its application, capability and limitations are discussed. Wafer dicing process results in edge and surface damage. Various characterization tools were used to detect these defects. Surface reflection topographs were taken to probe surface and subsurface defects, primarily scratches and micro cracks. Optical microscopy and SEM were used as a complementary tool for surface characterization. TEM is used for detecting sub-surface nano-cracks and dislocations. X-ray transmission topography is used to detect half loop dislocations resulting from dicing process. In order to study dynamic behavior of defects (dislocations) during thermal processing and operation an environmental chamber (furnace) is designed and built to record in-situ X-ray diffraction topographs during thermal cycling and at high temperature.