Through-Silicon Via (TSV) Related Noise Coupling in Three-Dimensional (3-D) Integrated Circuits (ICs)

Abstract

As conventional integrated circuits are approaching the physical limits due to technology scaling, alternative and complementary technologies have become a major focus. Among various emerging technologies, three-dimensional (3-D) integration technology offers several advantages to increase performance and functionality while reducing cost. In 3-D technologies, multiple dies are stacked in a monolithic fashion where the communication among the dies is achieved by vertical through-silicon vias (TSVs). Despite important advantages, 3-D integration has certain challenges that need to be addressed. In this thesis, noise coupling due to TSVs, an important issue that degrades signal integrity, is investigated. Compact models are proposed to analyze TSV related noise coupling for different TSV types such as via-first and via-last, and different substrate grounding topologies. Figures-of-merit and design guidelines are also developed to ensure reliable 3-D circuits in the presence of TSV related noise coupling.