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Power Distribution in 3-D Processor-Memory Stacks

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dc.contributor.advisor Salman, Emre en
dc.contributor.author Satheesh, Suhas M.
dc.contributor.other Department of Electrical Engineering. en
dc.date.accessioned 2012-10-10T16:17:28Z
dc.date.available 2012-10-10T16:17:28Z
dc.date.issued 2012-05-01
dc.date.submitted May-12 en
dc.identifier.uri http://hdl.handle.net/1951/57605
dc.description.abstract Three primary techniques for manufacturing through silicon vias (TSVs), viafirst, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with nine planes. Due to distinct fabrication techniques, these TSV technologies require significantly different design constraints, as investigated in this work. A valid design space that satisfies the peak power supply noise while minimizing area overhead is identified for each technology. It is demonstrated that the area overhead of a power distribution network with via-first TSVs is approximately 9% as compared to less than 2% in via-middle and via-last technologies. Despite this drawback, a via-first based power network is typically overdamped and the issue of resonance is alleviated. A via-last based power network, however, exhibits a relatively low damping factor and the peak noise is highly sensitive to number of TSVs and decoupling capacitance. en_US
dc.description.sponsorship Stony Brook University Libraries. Department of Electrical Engineering. Lawrence Martin (Dean of Graduate School). en_US
dc.format Electronic Resource. en
dc.language.iso en_US en_US
dc.publisher The Graduate School, Stony Brook University: Stony Brook, NY. en_US
dc.subject en_US
dc.subject.lcsh en
dc.subject.other 3-D IC, Decoupling capacitor, Peak noise, Power delivery, Processor-memory, TSV en
dc.title Power Distribution in 3-D Processor-Memory Stacks en_US
dc.type Thesis en_US
dc.description.advisor Advisor(S): Dr. Emre Salman Committee Member(s): Dr. Milutin Stanacevic. en


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