Now showing items 1-2 of 2

  • Power Distribution in 3-D Processor-Memory Stacks 

    Satheesh, Suhas M. (The Graduate School, Stony Brook University: Stony Brook, NY., 2012-05-01)
    Three primary techniques for manufacturing through silicon vias (TSVs), viafirst, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with ...
  • POWER DISTRIBUTION IN TSV BASED 3-D PROCESSOR-MEMORY STACKS 

    Satheesh, Suhas Mysore (The Graduate School, Stony Brook University: Stony Brook, NY., 1-May-12)
    Three primary techniques for manufacturing through silicon vias (TSVs), via-first, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with ...