Now showing items 1-1 of 1

    • POWER DISTRIBUTION IN TSV BASED 3-D PROCESSOR-MEMORY STACKS 

      Satheesh, Suhas Mysore (The Graduate School, Stony Brook University: Stony Brook, NY., 1-May-12)
      Three primary techniques for manufacturing through silicon vias (TSVs), via-first, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with ...