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    • Power Distribution in 3-D Processor-Memory Stacks 

      Satheesh, Suhas M. (The Graduate School, Stony Brook University: Stony Brook, NY., 2012-05-01)
      Three primary techniques for manufacturing through silicon vias (TSVs), viafirst, via-middle, and via-last, have been analyzed and compared to distribute power in a three-dimensional (3-D) processor-memory system with ...